1. Field of Invention
The present invention relates to an image processing circuit and image data processing method suitable for use with an electro-optical device, wherein image signals divided into multiple systems and extending in the time-axial direction and maintaining a constant signal level each unit time are supplied to the data lines at a predetermined timing, and to an electro-optical device using the same, and to an electronic apparatus.
2. Description of Related Art
A conventional electro-optical device, such as an active-matrix liquid crystal display device, is described with reference to FIG. 15 and FIG. 16. First, as shown in FIG. 15, the conventional liquid crystal display device comprises a liquid crystal display panel 100, a timing circuit 200, and an image signal processing circuit 300. Of these, the timing circuit 200 is for outputting timing signals described in greater detail below, to be used at each of the units. Also, a D/A converting circuit 301 within the image signal processing circuit 300 converts image data Da supplied from external equipment from digital signals into analog signals, and thus outputs image signals VID. Further, a phase rendering circuit 302 takes input of single-system image signals VID and can render the signals into N-phase (N=6 in the drawing) image signals, which are then output. The image signals can be rendered into N phases to extend the application time of image signals supplied to thin film transistors (hereafter referred to as xe2x80x9cTFTxe2x80x9d) in the later-described sampling circuit, thereby sufficiently securing sampling time for data signals in the TFT panel and discharging time thereof.
On the other hand, an amplifying/inverting circuit 303 inverts the polarity of image signals under the following conditions and amplifies the signals as appropriate, and then supplies the signals as phase-rendered image signals VID1 through VID6 to the liquid crystal display panel 100. Polarity inversion refers to a mutual inversion of voltage levels of the image signals, with the center potential of the amplitude thereof as the reference potential. Also, whether or not to perform inversion is determined according to whether the data signal application method is 1) polarity inversion in units of scanning lines, 2) polarity inversion in units of data signal lines, or 3) polarity inversion in units of pixels, and the inversion cycle thereof is set to one parallel scanning period or dot clock cycle.
Referring now to FIG. 16, the liquid crystal display panel 100 will be described. This liquid crystal display panel 100 is made up of a device substrate and opposing substrate facing one another across a gap, with liquid crystal filled in this gap. Now, the device substrate and opposing substrate can be formed of quartz substrate, hard glass, or the like.
Of these, regarding the device substrate, multiple scanning lines 112 are arrayed in parallel in the X direction in FIG. 16, and orthogonal to this, multiple data lines 114 are arrayed in parallel in the Y direction. Now, the data lines 114 are blocked in units of 6 lines, forming what will be called blocks B1 through Bm. In the following for the sake of facilitating description, reference to data lines in general will be made with the denoting reference numeral as 114, but reference numerals 114a through 114f will be used in the event of indicating specific data lines.
The gate electrode of each TFT 116, serving as a switching device for example, is connected to each intersection between the scanning lines 112 and data lines 114, while the source electrodes of the TFTs 116 are connected to the data lines 114, and the drain electrodes of the TFTs 116 are connected to the pixel electrodes 118. Each pixel is made up of a pixel electrode 118, a shared electrode formed on the opposing substrate, and the liquid crystal sandwiched between these electrodes, forming a matrix array at each intersection between the scanning lines 112 and data lines 114. Also, holding capacity (omitted in drawing) is formed in a state connected to each pixel electrode 118.
Now, a scanning driving circuit 120 is formed on the device substrate, so as to sequentially output pulse scanning signals to the scanning lines 112, based on the clock signals CLY from the timing circuit 200, inverted clock signals thereof CLYinv, transfer starting pulses DY, etc. In more detail, the scanning driving circuit 120 sequentially shifts the transfer starting pulses DY supplied at the start of the vertical scanning period according to the clock signal CLY and the inverted clock signals thereof CLYinv, and outputs these as scanning line signals, whereby the scanning lines 112 are sequentially selected.
On the other hand, the sampling circuit 130 has one sampling switch 131 for each data line 114 at the end of the data lines 114. The switches 131 are formed of TFTs formed on the same device substrate, and image signals VID1 through VID6 are input to the source electrodes of the switches 131 via the image signals supplying lines L1 through L6. The gate electrodes of the six switches 131 connected to the data lines 114a through 114f of block B1 are connected to signals lines to which sampling signals S1 are supplied, the gate electrodes of the six switches 131 connected to the data lines 114a through 114f of block B2 are connected to signals lines to which sampling signals S2 are supplied, and so on up to the gate electrodes of the six switches 131 connected to the data lines 114a through 114f of block Bm being connected to signals lines to which sampling signals Sm are supplied. Now, the sampling signals S1 through Sm are each for sampling the image signals VID1 through VID6 by block within a horizontal valid display period.
Also, the shift register circuit 140 is formed on the same device substrate, and sequentially outputs the sampling signals S1 through Sm based on the clock signals CLX, the inverted clock signals thereof CLXinv, and the transfer starting pulses DX and the like from the timing circuit 200. In more detail, the shift register circuit 140 sequentially shifts the transfer starting pulses DX supplied at the beginning of the horizontal scanning period according to the clock signals CLX and the inverted clock signals thereof CLXinv, and sequentially outputs these as sampling signals S1 through Sm.
With such a configuration, at the point that the sampling signal S1 is output, the six data lines 114a through 114f belonging to the block B1 have the image signals VID1 through VID6 thereof sampled, and the image signals VID1 through VID6 are each written to the six pixels of the scanning line currently selected by the corresponding TFTs 116.
Subsequently, at the point that the sampling signal S2 is output, the six data lines 114a through 114f belonging to the block B2 have the image signals VID1 through VID6 thereof sampled, and the image signals VID1 through VID6 are each written to the six pixels of the scanning line selected by the corresponding TFTs 116 at that point.
In the same way, at the point that the sampling signals S3, S4, and so on through Sm are sequentially output, the six data lines 114a through 114f belonging to the blocks B3, B4, and so on through Bm have the image signals VID1 through VID6 thereof sampled, and the image signals VID1 through VID6 are each written to the six pixels of the scanning lines currently selected by the corresponding TFTs 116. Then, the next scanning line is selected, and the same writing is executed at the blocks B1 through Bm repeatedly.
With this driving method, the number of tiers of the shift register circuit 140 for performing driving controlling of the switches 131 of the sampling circuit 130 is reduced to ⅙, as compared to the method wherein the data lines are driven according to point sequence. Further, the frequency of the clock signals CLX and the inverted clock signals thereof CLXinv to be supplied to the shift register circuit 140 is also reduced to ⅙, thus reducing electric power consumption along with reducing the number of tiers.
However, the above-described conventional device suffers from the drawback that when one-system image signals are phase rendered into multiple systems and the liquid crystal display panel is driven using the multiple system image signals, a light image of the same form as the original image is displayed at a position slightly offset from the display position of the original image. This phenomena will be referred to as xe2x80x9cghostingxe2x80x9d.
There are various causes for ghosting, however, as described below, there are two causes that are uniquely characteristic to phase rendering. A first cause is that the image signal supplying lines L1 through L6 equivalently configure a low-pass filter. In other words, as shown in FIG. 15, the image signal supplying lines L1 through L6 extend in the X direction from the right end of the liquid crystal display panel 100 to the left end thereof, such that a distributed resistance exists there, accompanied by floating capacity. Accordingly, the image signal supplying lines L1 through L6 equivalently make up a low-pass filter. Thus, the waveforms of the image signals VID1 through VID6 input to the switches 131 of the sampling circuit 130 become integrated waveforms. This point is described in greater detail.
FIG. 17 is a timing chart illustrating the waveform of image signals and sampling signals before and following phase rendering. Now, though delay actually occurs along with the phase rendering, the figure ignores the delay time for the sake of clarity. Note that the liquid crystal display panel 100 operates in the normally-white mode.
As shown in graph (a) of FIG. 17, in the event that the image signal VID corresponds to the blocks Jxe2x88x921xe2x80x2th through J+1xe2x80x2th, and is at the intermediate level Vc at the periods t1 through t3, is at the black level Vb at the periods t4 through t14, and is at the intermediate level Vc at the periods t15 through t18, the image signals VID1 through VID6 following rendering will be as shown by graphs (b) through (g) in the figure.
For example, taking note of the image signal VID3 shown in graph (d) in the figure, the image signal VID is at the intermediate level Vc at the period t3, and is at the black level Vb at the period t9, so ignoring the delay time, the image signal VID3 should at the start of the period t7 rapidly rise up from the intermediate level Vc to the black level Vb as shown by the dotted line in the figure. However, as described above, the image signal supplying line L3 equivalently forms a low-pass filter as described above, so the image signal VID3 gradually rises up from the intermediate level Vc, and reaches the black level Vb after a certain amount of time.
Accordingly, assuming that the sampling signal Sj corresponding to the jxe2x80x2th block becomes active in the range from period t7 through period t12 as shown by (h) in the figure, the image signal VID3 supplied to the data line 114c of the jxe2x80x2th block is affected by the image signal VID3 to be supplied to the data line 114c of the jxe2x88x921xe2x80x2th block (VID3 in periods t1 through t6). Consequently, taking in the voltage of this data line 114c with the TFT 112 making up the pixel causes the voltage value to drop somewhat below the black level, and the pixel becomes somewhat lighter.
Further, assuming that the sampling signal Sj corresponding to the jxe2x80x2th block becomes active in the range from period t7 through period t13 as shown by graph (i) in the figure, the image signal VID3 supplied to the data line 114c of the jxe2x80x2th block is affected by not only the image signal VID3 to be supplied to the data line 114c of the jxe2x88x921xe2x80x2th block (image signal VID3 in periods t1 through t6) but also the image signal VID3 to be supplied to the data line 114c of the j+1xe2x80x2th block (image signal VID3 in periods t13 through t18).
FIG. 18 is an explanatory diagram illustrating an example of ghosting due to the above-described first cause. In this diagram, the image that should originally be displayed is the arrow P. In relation to this, the arrow P1 and the arrow P2 which are lightly displayed at positions one block before and behind, are ghosts.
Next, the second cause of ghosting is that there is parasitic capacity accompanying each of the data lines 114a through 114f of each of the blocks B1, B2, and so on through Bm, and that the parasitic capacities are joined. As described above, the data lines 114a through 114f are formed on the device substrate, and face the facing electrode on the facing substrate across the liquid crystal, and thus parasitic capacity primarily with the opposing electrode occurs. Also, the opposing electrode is grounded with a predetermined impedance. Accordingly, the parasitic capacities of the data lines 114a through 114f are Ca through Cf, and with the impedance of the opposing electrode as R, the equivalency circuit of the data lines 114a through 114f is as shown in FIG. 19.
Now, in the event that the image signal VID3 supplied to the data line 114c changes from the black level Vb to the intermediate level Vc at upon switching of blocks, the voltage Vx of the shared contact of the parasitic capacities Ca through Cf is the image signal VID3 differentiated, as shown in FIG. 20. This results in the voltage of the data lines 114a, 114b, and 114d through 114f changing via the parasitic capacities Ca, Cb, and Cd through Cf.
For example, let us assume an arrangement such as shown in FIG. 21 wherein one screen is configured of blocks B1 through B7, and one vertical black straight line is displayed on an intermediate gradient background. In this case, in the event that the image signal VID3 of the black level Vb is supplied to the data line 114c of the block B4, the image signal VID3 changes from the black level Vb to the intermediate level Vc at the point of switching from block B4 to block B5. This causes the voltage of the data lines 114a, 114b, and 114d through 114f of block B4 to be affected by the differentiated waveform (see FIG. 20), and rises slightly higher than the voltage corresponding to the intermediate gradient, so the overall block B5 becomes somewhat brighter. Thus, the method of forming blocks of the data lines 114 for driving has had the problem of the quality of the displayed image deteriorating due to the above two types of ghosts.
The present invention has been made in light of these problems, and accordingly it is an object to provide an image processing circuit and image data processing method enabling high-quality display by removing ghosts, an electro-optical device using the same, and an electronic apparatus.
To this end, an image processing circuit according to the present invention comprises a delay circuit for delaying externally supplied image data by a unit time and outputting as first delayed image data, a difference circuit for generating the difference between the first delayed image data and the image data as difference image data, a multiplying circuit for multiplying the difference image data by a coefficient and generating correction data, a generating circuit for synthesizing the image data and the correction data to generate corrected image data, and a phase rendering circuit that divides the corrected image data being input in a time-sequence in to a plurality of phases.
In accordance with the present invention, images are displayed based on image signals divided into multiple systems and extended in the time-axial direction, which maintain a constant signal level each unit time, but floating capacity can exist on the lines for supplying the image signals to the data lines. Accordingly, the waveform of the image signals supplied to the data lines are affected by the floating capacity, and can thus become less sharp. In this case, the image signals in the current unit time are affected by the image signals in the unit time immediately before. According to the present invention, with the image data as the current data, first delayed image data is equivalent to past data by one unit time, and corrected data is generated based on the difference image data thereof. That is to say, the corrected data predicts waveform deterioration of the image signals beforehand. The corrected image data is synthesized based on the correction data and the image data, and accordingly waveform deterioration is generated in the process until image signals supplied to the data lines can be cancelled, by generating image signals based on the corrected image data. Consequently, ghosting due to floating capacity on the lines can be markedly reduced, and the quality of the displayed image can be greatly improved.
Now, the electro-optical device preferably comprises a plurality of switching devices for sampling image signals subjected to phase rendering according to sampling signals and supplying to the data lines, and image signals supplying lines for supplying the image signals to the switching devices, wherein the coefficient is determined according to low-pass filter properties configured equivalently by the image signals supplying lines. Further, the active period of the sampling signals preferably ends within the current unit time of the image signals.
The high-frequency component lost by the image signals being sent over the image signal supplying lines is dependent on the difference level of the image signals in the current and immediately-preceding unit times, and on the properties of the low-pass filter. The data value of the difference image data is equivalent to the difference level, so this multiplied by a coefficient corresponding to the properties of the low pass filter is equivalent to the high-frequency component lost due to the image signal supplying lines. According to the present invention, the coefficient is determined according to the low-pass filter properties, so that correction data, accurately predicting the high-frequency component which will be lost by the image signals being sent over the image signal supplying lines, can be generated.
Next, an image data processing method according to the present invention comprises a step for delaying externally supplied current image data by a unit time and generating past image data; a step for generating correction data based on the difference in data values between the current image data and the past image data; a step for synthesizing the current image data and the correction data to generate corrected image data; and a step for dividing the corrected image data into multiple systems and extending in the time-axial direction, and supplying the image signals maintaining a constant signal level each unit time at a predetermined timing, to a plurality of data lines.
According to the present invention, the correction data can be generated based on the current image data and past image data by one unit time, so that the correction data predicts waveform deterioration of the image signals beforehand. The corrected image data is synthesized based on the correction data and the image data, and accordingly waveform deterioration generated in the process until image signals are supplied to the data lines can be cancelled, by generating image signals based on the corrected image data. Consequently, ghosting due to floating capacity on the lines can be markedly reduced, and the quality of the displayed image can be greatly improved.
Next, an image processing circuit according to the present invention comprises a first delay circuit for delaying externally supplied image data by a unit time of the image signals and outputting as first delayed image data; a second delay circuit for delaying the first delayed image data by a unit time of the image signals and outputting as second delayed image data; a first difference circuit for generating the difference between the first delayed image data and the second delayed image data as first difference image data; a first multiplying circuit for multiplying the first difference image data by a first coefficient and generating first correction data; a second difference circuit for generating the difference between the first delayed image data and the image data as second difference image data; a second multiplying circuit for multiplying the second difference image data by a second coefficient and generating second correction data; a synthesizing circuit for synthesizing the first delayed image data, the first correction data, and the second correction data, to generate corrected image data; and a phase rendering circuit that divides the corrected image data being input in a time-sequence in to a plurality of phases.
According to the present invention, the first delay circuit and the second delay circuit can each delay image data by unit time, so with the first delayed image data as the current data, the image data is equivalent to future data, and the second delayed image data is equivalent to past data. Accordingly, the current data can be corrected based on not only past data, but also future data, thereby generating corrected image data.
Now, the electro-optical device preferably comprises a plurality of switching devices for sampling image signals subjected to phase rendering according to sampling signals and supplying to the data lines, and image signals supplying lines for supplying the image signals to the switching devices, wherein the first coefficient and the second coefficient are determined according to low-pass filter properties configured equivalently by the image signals supplying lines. Further, the active period of the sampling signals preferably starts in the current unit time of the image signals and ends in the next unit time.
The voltage of the data lines is determined at the ending point of the active period of the sampling signals, so in the event that the active period of the sampling signals ends at the next unit time, the voltage of the data line is affected by the image signals of the next unit time. According to the present invention, corrected data is generated by correcting the current data based not only on the past but also on future data, so image signals can be generated based on the corrected image data, and accordingly waveform deterioration generated in the process until image signals are supplied to the data lines can be cancelled by generating image signals based on the corrected image data. Consequently, ghosting due to floating capacity on the lines can be markedly reduced, and the quality of the displayed image can be greatly improved.
Next, an image data processing method according to the present invention comprises a step for taking externally supplied image data as future image data and sequentially delaying this by a unit time so as to generate current image data and past image data; a step for generating first correction data based on difference data value between the current image data and the past image data; a step for generating second correction data based on difference data value between the current image data and the future image data; a step for synthesizing the current image data, the first correction data, and the second correction data, to generate corrected image data; and a step for dividing the corrected image data into multiple systems and extending in the time-axial direction, and supplying the image signals maintaining a constant signal level each unit time at a predetermined timing, to a plurality of data lines.
According to the present invention, the current image data can be corrected based on not only past data but also future data, thereby generating corrected image data.
Next, an image processing circuit according to the present invention comprises a delay circuit for delaying externally supplied image data by a unit time and outputting as delayed image data; a difference circuit for generating the difference between the delayed image data and the image data as difference image data; an averaging circuit for averaging the difference image data each unit time and generating averaged image data; a correcting circuit for correcting the delayed image data based on the averaged image data and generating corrected image data; and a phase rendering circuit that divides the corrected image data being input in a time-sequence in to a plurality of phases.
Parasitic capacity accompanies each of the data lines, and further data lines in close proximity are joined via the parasitic capacity, and the parasitic capacities are grounded via an equivalently shared impedance. Accordingly, in the event that the applied voltage of a particular data line changes, the potential of other data lines changes due to being affected thereby, and ghosts corresponding thereto occur. According to the invention described above, correction data is generated based on the averaged image data obtained by averaging the difference image data by each unit time, so the correction data is of a component corresponding to the above-described ghosts. Accordingly, the corrected image data predicts ghosts beforehand and can cancel the component thereof. Consequently, displaying the image based on corrected image data enables the ghosts to be almost done away with, thereby markedly improving the quality of the displayed image.
Now, the averaging circuit preferably comprises an accumulating adder for accumulating and adding the difference image data each unit time, and a divider for dividing the output data of the accumulating adder by the number of the plurality of systems. Further, the correcting circuit preferably comprises a coefficient unit for multiplying the averaged image data by a coefficient, and an adder for adding the delayed image data and the output data of the coefficient unit.
Next, an image data processing method according to the present invention comprises a step for delaying externally supplied image data by a unit time and generating as delayed image data; a step for generating the difference between the delayed image data and the image data as difference image data; a step for averaging the difference image data each unit time and generating averaged image data; a step for correcting the delayed image data based on the averaged image data and generating corrected image data; and a step for dividing the corrected image data into multiple systems and extending in the time-axial direction, and supplying the image signals maintaining a constant signal level each unit time at a predetermined timing, to a plurality of data lines.
According to the present invention, correction data can be generated predicting beforehand ghost components occurring due to capacity joining of data lines in close proximity. Accordingly, the corrected image data predicts ghosts beforehand and can cancel the component thereof. Consequently, displaying the image based on corrected image data enables the ghosts to be mostly removed, thereby markedly improving the quality of the displayed image.
Next, an electro-optical device according to the present invention comprises an above-described image processing circuit; an image signal generating circuit for generating image signals divided into multiple systems and extended in the time-axial direction and maintaining a constant signal level each unit time, based on the corrected image data; a data line driving circuit for sequentially generating the sampling signals; and a sampling circuit for sampling the image signals based on the sampling signals and supplies to the data lines. According to this electro-optical device, the quality of the displayed image can be greatly improved, and also the time of supplying image signals to the data lines can be extended.
Next, an electronic apparatus according to the present invention comprises an above-described electro-optical device, and is such as a video projector, notebook type personal computer, cellular phone, or the like.